revert bug in icache wishbone ack

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 4788fda26f2680f50325090e13d7e2bbf8ad8d73..46ba5d0cddb409c4362041578255bc532a9a7e5d 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -926,6 +926,18 @@ class ICache(Elaboratable):
                         sync += r.wb.stb.eq(0)
                         comb += stbs_done.eq(1)
 
+                    # Calculate the next row address
+                    rarange = Signal(LINE_OFF_BITS - ROW_OFF_BITS)
+                    comb += rarange.eq(
+                             r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1
+                            )
+                    sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq(
+                             rarange
+                            )
+                    sync += Display("RARANGE r.req_adr:%x rarange:%x "
+                                    "stbs_zero:%x stbs_done:%x",
+                                    r.req_adr, rarange, stbs_zero, stbs_done)
+
                 # Incoming acks processing
                 with m.If(wb_in.ack):
                     sync += Display("WB_IN_ACK data:%x stbs_zero:%x "
@@ -956,20 +968,6 @@ class ICache(Elaboratable):
                         # Increment store row counter
                         sync += r.store_row.eq(next_row(r.store_row))
 
-                        # Calculate the next row address
-                        rarange = Signal(LINE_OFF_BITS - ROW_OFF_BITS)
-                        comb += rarange.eq(
-                                 r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1
-                                )
-                        sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq(
-                                 rarange
-                                )
-                        sync += Display("RARANGE r.req_adr:%x rarange:%x "
-                                        "stbs_zero:%x stbs_done:%x",
-                                        r.req_adr, rarange,
-                                        stbs_zero, stbs_done)
-
-
         # TLB miss and protection fault processing
         with m.If(flush_in | m_in.tlbld):
             sync += r.fetch_failed.eq(0)