use copy of FHDLTestCase

[soc.git] / src / soc / experiment / proof_datamerger.py

diff --git a/src/soc/experiment/proof_datamerger.py b/src/soc/experiment/proof_datamerger.py
index cfa936e1cfb0241201a3fce0b4f5d36aa57d1b5d..6fe7aead21686c3e24b30e0d69841060c39eb4f3 100644 (file)
--- a/src/soc/experiment/proof_datamerger.py
+++ b/src/soc/experiment/proof_datamerger.py
@@ -5,7 +5,7 @@
 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed)
 from nmigen.asserts import Assert, AnyConst, AnySeq, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from soc.experiment.l0_cache import DataMerger