add some data for MMU to actually look up

[soc.git] / src / soc / experiment / test / test_ldst_pi.py

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index cd9a6773db6c8bf1a928544ccbc355de269f8148..290cbf5e081138d922a497efd52f500775d5e304 100644 (file)
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -54,6 +54,9 @@ def wb_get(wb):
           0x1000000:   # PROCESS_TABLE_3
                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
            b(0x40000000000300ad),
+
+         # data to return
+          0x1000: 0xdeadbeef01234567
           }
 
     while not stop:
@@ -82,8 +85,8 @@ def mmu_lookup(dut, addr):
     global stop
 
     print("pi_ld")
-    yield from pi_ld(dut.submodules.ldst.pi, addr, 1, msr_pr=1)
-    print("pi_ld done")
+    data = yield from pi_ld(dut.submodules.ldst.pi, addr, 4, msr_pr=1)
+    print("pi_ld done, data", hex(data))
     """
     # original test code kept for reference
     while not stop: # wait for dc_valid / err
@@ -119,17 +122,16 @@ def ldst_sim(dut):
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
     yield
 
-    addr = 0x10000
-    data = 0
-    print("pi_st")
+    addr = 0x1000
+    print("pi_ld")
 
     # TODO mmu_lookup using port interface
     # set inputs 
-    phys_addr = yield from mmu_lookup(dut, 0x10000)
-    assert phys_addr == 0x40000
+    phys_addr = yield from mmu_lookup(dut, addr)
+    #assert phys_addr == addr # happens to be the same (for this example)
 
-    phys_addr = yield from mmu_lookup(dut, 0x10000)
-    assert phys_addr == 0x40000
+    phys_addr = yield from mmu_lookup(dut, addr)
+    #assert phys_addr == addr # happens to be the same (for this example)
 
     stop = True
 
@@ -138,8 +140,8 @@ def test_mmu():
 
     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
                          imem_ifacetype='',
-                         disable_cache=True,
                          addr_wid=48,
+                         #disable_cache=True, # hmmm...
                          mask_wid=8,
                          reg_wid=64)