fix wb_get error where data was being corrupted

[soc.git] / src / soc / experiment / test / test_mmu_dcache.py

diff --git a/src/soc/experiment/test/test_mmu_dcache.py b/src/soc/experiment/test/test_mmu_dcache.py
index aab6dcec9757bc52eb5668301bb4365991c43b6e..1528d7d40db31bbaed8f821a7a90663ef087bb26 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache.py
+++ b/src/soc/experiment/test/test_mmu_dcache.py
@@ -22,13 +22,20 @@ from soc.experiment.mmu import MMU
 from soc.experiment.dcache import DCache
 from soc.experiment.icache import ICache
 
-from random import randint
+import random
 
 stop = False
 
+def set_stop(newval):
+    global stop
+    stop = newval
+
+
 def b(x):
     return int.from_bytes(x.to_bytes(8, byteorder='little'),
                           byteorder='big', signed=False)
+
+
 default_mem = { 0x10000:    # PARTITION_TABLE_2
                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
                 b(0x800000000100000b),
@@ -52,14 +59,17 @@ def wb_get(c, mem, name):
     """simulator process for getting memory load requests
     """
 
-    global stop
-
+    logfile = open("/tmp/wb_get.log","w")
 
-    mem = mem
+    def log(msg):
+        logfile.write(msg+"\n")
+        print(msg)
 
+    global stop
     while not stop:
         while True: # wait for dc_valid
             if stop:
+                log("stop")
                 return
             cyc = yield (c.wb_out.cyc)
             stb = yield (c.wb_out.stb)
@@ -68,17 +78,18 @@ def wb_get(c, mem, name):
             yield
         addr = (yield c.wb_out.adr) << 3
         if addr not in mem:
-            print ("    %s LOOKUP FAIL %x" % (name, addr))
+            log("%s LOOKUP FAIL %x" % (name, addr))
             stop = True
             return
 
         yield
         data = mem[addr]
         yield c.wb_in.dat.eq(data)
-        print ("    %s get %x data %x" % (name, addr, data))
+        log("%s get %x data %x" % (name, addr, data))
         yield c.wb_in.ack.eq(1)
         yield
         yield c.wb_in.ack.eq(0)
+        yield
 
 
 def icache_sim(dut, mem):
@@ -126,8 +137,12 @@ def test_icache_il():
 def test_icache():
     # create a random set of addresses and "instructions" at those addresses
     mem = {}
-    for i in range(100):
-        mem[randint(0, 1<<10)] = b(randint(0,1<<32))
+    # fail 'AssertionError: insn @1d8=0 expected 61928a6100000000'
+    #random.seed(41)
+    # fail infinite loop 'cache read adr: 24 data: 0'
+    random.seed(43)
+    for i in range(3):
+        mem[random.randint(0, 1<<10)] = b(random.randint(0,1<<32))
 
     # set up module for simulation
     m = Module()
@@ -211,5 +226,5 @@ def test_mmu():
 
 if __name__ == '__main__':
     test_mmu()
-    test_icache_il()
+    #test_icache_il()
     #test_icache()