fix wb_get error where data was being corrupted

[soc.git] / src / soc / experiment / test / test_mmu_dcache_pi.py

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index 0dc182b290bb890757718337853dfe84464bcac9..2f219e63ebbd91043a54f81d8f06f88e9eaf7939 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -1,3 +1,9 @@
+"""MMU PortInterface Test
+
+quite basic, calls pi_ld to get data via PortInterface.  this test
+shouldn't really exist, it's superceded by test_ldst_pi.py
+"""
+
 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
 from nmigen.cli import main
 from nmigen.cli import rtlil
@@ -43,29 +49,30 @@ from nmigen.compat.sim import run_simulation, Settle
 # will take at least one week (10.10.2020)
 # many unconnected signals
 
+
 class TestMicrowattMemoryPortInterface(PortInterfaceBase):
     """TestMicrowattMemoryPortInterface
 
     This is a Test Class for MMU and DCache conforming to PortInterface
     """
 
-    def __init__(self, mmu, dcache, regwid=64, addrwid=4,):
+    def __init__(self, mmu, dcache, regwid=64, addrwid=4):
         super().__init__(regwid, addrwid)
         self.mmu = mmu
         self.dcache = dcache
 
-    def set_wr_addr(self, m, addr, mask, misalign):
+    def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
         m.d.comb += self.dcache.d_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.load.eq(0)
-        m.d.comb += self.mmu.l_in.priv.eq(1)
+        m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here
         m.d.comb += self.mmu.l_in.valid.eq(1)
 
-    def set_rd_addr(self, m, addr, mask, misalign):
+    def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
         m.d.comb += self.dcache.d_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.load.eq(1)
-        m.d.comb += self.mmu.l_in.priv.eq(1)
+        m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here
         m.d.comb += self.mmu.l_in.valid.eq(1)
 
     def set_wr_data(self, m, data, wen):
@@ -89,6 +96,7 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase):
         data = self.dcache.d_out.data
         return data, ld_ok
 
+
         # DCacheToLoadStore1Type NC
         # store_done
         # error
@@ -154,26 +162,24 @@ def wb_get(dc):
             yield
         addr = (yield dc.wb_out.adr) << 3
         if addr not in mem:
-            print ("    DCACHE LOOKUP FAIL %x" % (addr))
-            stop = True
-            return
+            print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
 
-        yield
-        data = mem[addr]
+        data = mem.get(addr, 0)
         yield dc.wb_in.dat.eq(data)
         print ("    DCACHE get %x data %x" % (addr, data))
         yield dc.wb_in.ack.eq(1)
         yield
         yield dc.wb_in.ack.eq(0)
+        yield
 
 
 def mmu_lookup(dut, addr):
     mmu = dut.mmu
     global stop
 
-    print("pi_st")
+    print("pi_ld")
     yield from pi_ld(dut.pi, addr, 1)
-    print("pi_st_done")
+    print("pi_ld done")
     """
     # original test code kept for reference
     while not stop: # wait for dc_valid / err
@@ -222,6 +228,7 @@ def mmu_sim(dut):
 
     stop = True
 
+
 def test_mmu():
     mmu = MMU()
     dcache = DCache()
@@ -239,5 +246,6 @@ def test_mmu():
     with sim.write_vcd('test_mmu_pi.vcd'):
         sim.run()
 
+
 if __name__ == '__main__':
     test_mmu()