add readonly option to TestMemory

[soc.git] / src / soc / experiment / testmem.py

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 4821e21d3fcc9aa3b141717a8c9f19c7ab3284ee..bf7c7e3b599ed01b6d734e6c1bfa1d31b230b97e 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -2,26 +2,38 @@ from nmigen import Module, Elaboratable, Memory
 
 
 class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw, granularity=None):
+    def __init__(self, regwid, addrw, granularity=None, init=True,
+                                      readonly=False):
+        self.readonly = readonly
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.depth = depth
         self.regwid = regwid
-        self.mem   = Memory(width=regwid, depth=depth,
-                            init=range(0, depth*2, 2))
+        print ("test memory", regwid, depth)
+        if init is True:
+            init = range(0, depth*2, 2)
+        else:
+            init = None
+        self.mem = Memory(width=regwid, depth=depth, init=init)
         self.rdport = self.mem.read_port() # not now transparent=False)
+        if self.readonly:
+            return
         self.wrport = self.mem.write_port(granularity=granularity)
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.rdport = self.rdport
+        if self.readonly:
+            return m
         m.submodules.wrport = self.wrport
         return m
 
     def __iter__(self):
         yield self.rdport.addr
         yield self.rdport.data
-        yield self.rdport.en
+        #yield self.rdport.en
+        if self.readonly:
+            return
         yield self.wrport.addr
         yield self.wrport.data
         yield self.wrport.en