big reorg on PowerDecoder2, actually Decode2Execute1Type

[soc.git] / src / soc / fu / alu / alu_input_record.py

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 472eaaf4c988635cd532e1de00a1d6e3cac6c516..18ef6ad42e52105ac3961cb9abd2f81f5089e419 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -20,7 +20,7 @@ class CompALUOpSubset(Record):
                   ('invert_a', 1),
                   ('zero_a', 1),
                   ('invert_out', 1),
-                  ('write_cr', Layout((("data", 3), ("ok", 1)))), # Data
+                  ('write_cr0', 1),
                   ('input_carry', CryIn),
                   ('output_carry', 1),
                   ('input_cr', 1),
@@ -56,7 +56,7 @@ class CompALUOpSubset(Record):
         """
         res = []
         for fname, sig in self.fields.items():
-            eqfrom = other.fields[fname]
+            eqfrom = other.do.fields[fname]
             res.append(sig.eq(eqfrom))
         return res