rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / fu / alu / formal / proof_input_stage.py

diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index 0d664a750c872915ab421f58f6173088b48a0b79..afa39b1319b54c42134f55d7409efb46280c1642 100644 (file)
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -51,7 +51,7 @@ class Driver(Elaboratable):
             dut_sig = getattr(dut.o.ctx.op, name)
             comb += Assert(dut_sig == rec_sig)
 
-        with m.If(rec.invert_a):
+        with m.If(rec.invert_in):
             comb += Assert(dut.o.a == ~a)
         with m.Else():
             comb += Assert(dut.o.a == a)