from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
signed)
from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
from soc.fu.alu.main_stage import ALUMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from openpower.decoder.power_enums import MicrOp
import unittest
width = p.width
comb += p.eq(AnyConst(width))
- pspec = ALUPipeSpec(id_wid=2)
+ pspec = ALUPipeSpec(id_wid=2, parent_pspec=None)
m.submodules.dut = dut = ALUMainStage(pspec)
# convenience variables
a = dut.i.a
b = dut.i.b
ca_in = dut.i.xer_ca[0] # CA carry in
- ca32_in = dut.i.xer_ca[1] # CA32 carry in 32
+ ca32_in = dut.i.xer_ca[1] # CA32 carry in 32
so_in = dut.i.xer_so # SO sticky overflow
ca_o = dut.o.xer_ca.data[0] # CA carry out
- ca32_o = dut.o.xer_ca.data[1] # CA32 carry out32
+ ca32_o = dut.o.xer_ca.data[1] # CA32 carry out32
ov_o = dut.o.xer_ov.data[0] # OV overflow
- ov32_o = dut.o.xer_ov.data[1] # OV32 overflow32
+ ov32_o = dut.o.xer_ov.data[1] # OV32 overflow32
o = dut.o.o.data
# setup random inputs
ca_in.eq(AnyConst(0b11)),
so_in.eq(AnyConst(1))]
+ # and for the context muxid
+ width = dut.i.ctx.muxid.width
+ comb += dut.i.ctx.muxid.eq(AnyConst(width))
+
+ # assign the PowerDecode2 operation subset
comb += dut.i.ctx.op.eq(rec)
- # Assert that op gets copied from the input to output
- for rec_sig in rec.ports():
- name = rec_sig.name
- dut_sig = getattr(dut.o.ctx.op, name)
- comb += Assert(dut_sig == rec_sig)
+ # check that the operation (op) is passed through (and muxid)
+ comb += Assert(dut.o.ctx.op == dut.i.ctx.op)
+ comb += Assert(dut.o.ctx.muxid == dut.i.ctx.muxid)
# signed and signed/32 versions of input a
a_signed = Signal(signed(64))
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_ADD):
+ with m.Case(MicrOp.OP_ADD):
# check result of 65-bit add-with-carry
comb += Assert(Cat(o, ca_o) == (a + b + ca_in))
comb += ca_ok.eq(1)
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_EXTS):
+ with m.Case(MicrOp.OP_EXTS):
for i in [1, 2, 4]:
with m.If(rec.data_len == i):
# main part, then sign-bit replicated up
comb += Assert(o[i*8:64] == Repl(a[i*8-1], 64-(i*8)))
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_CMP):
+ with m.Case(MicrOp.OP_CMP):
# CMP is defined as not taking in carry
comb += Assume(ca_in == 0)
comb += Assert(o == (a+b)[0:64])
- with m.Case(InternalOp.OP_CMPEQB):
+ with m.Case(MicrOp.OP_CMPEQB):
src1 = a[0:8]
eqs = Signal(8)
for i in range(8):
module = Driver()
self.assertFormal(module, mode="bmc", depth=2)
self.assertFormal(module, mode="cover", depth=2)
+
def test_ilang(self):
dut = Driver()
vl = rtlil.convert(dut, ports=[])