from nmigen import Module, Signal, Elaboratable, Mux, Cat, signed
from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
from soc.fu.alu.output_stage import ALUOutputStage