add LGPLv3+ notice and add copyright holders

[soc.git] / src / soc / fu / alu / main_stage.py

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 7f98c344535ea6665262afb2f71fb4e8e4f0f18c..9e282c8c4c503b66254fde827955a009e88349e9 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -4,7 +4,11 @@
 # however should not gate the carry or overflow, that's up to the
 # output stage
 
+# License: LGPLv3+
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# (michael: note that there are multiple copyright holders)
+
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts, extz
@@ -60,7 +64,10 @@ class ALUMainStage(PipeModBase):
 
         a_i = Signal.like(a)
         b_i = Signal.like(b)
-        with m.If(is_32bit):
+        with m.If(op.insn_type == MicrOp.OP_CMP): # another temporary hack
+            comb += a_i.eq(a)                     # reaaaally need to move CMP
+            comb += b_i.eq(b)                     # into trap pipeline
+        with m.Elif(is_32bit):
             with m.If(op.is_signed):
                 comb += a_i.eq(exts(a, 32, 64))
                 comb += b_i.eq(exts(b, 32, 64))