# however should not gate the carry or overflow, that's up to the
# output stage
+# License: LGPLv3+
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# (michael: note that there are multiple copyright holders)
+
from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
from nmutil.pipemodbase import PipeModBase
from nmutil.extend import exts, extz
a_i = Signal.like(a)
b_i = Signal.like(b)
- with m.If(is_32bit):
+ with m.If(op.insn_type == MicrOp.OP_CMP): # another temporary hack
+ comb += a_i.eq(a) # reaaaally need to move CMP
+ comb += b_i.eq(b) # into trap pipeline
+ with m.Elif(is_32bit):
with m.If(op.is_signed):
comb += a_i.eq(exts(a, 32, 64))
comb += b_i.eq(exts(b, 32, 64))
# this is supposed to be inverted (b-a, not a-b)
comb += a_n.eq(~a) # sigh a gets inverted
- comb += carry_32.eq(add_o[33] ^ a_n[32] ^ b[32])
+ comb += carry_32.eq(add_o[33] ^ a[32] ^ b[32])
comb += carry_64.eq(add_o[65])
comb += zerolo.eq(~((a_n[0:32] ^ b[0:32]).bool()))