normalise XER regs carry/32 and SO

[soc.git] / src / soc / fu / alu / output_stage.py

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 08946de12cb5e8dc3ab0d0fa67a6d92ec27a7026..8b95334702bcc2d0969a017e1fab312c165c09a0 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -38,8 +38,8 @@ class ALUOutputStage(PipeModBase):
             comb += target.eq(o)
 
         # Handle carry_out
-        comb += self.o.xer_co.data.eq(self.i.xer_co.data)
-        comb += self.o.xer_co.ok.eq(op.output_carry)
+        comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
+        comb += self.o.xer_ca.ok.eq(op.output_carry)
 
         # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)