mass-rename of modules to soc.fu.*

[soc.git] / src / soc / fu / alu / output_stage.py

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 1253795708f6f4e86c01378c0a1eca7a4cca441c..c93fec5be47e8d04ba646a57292ef789f17e1cb0 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -3,7 +3,7 @@
 # register
 from nmigen import (Module, Signal, Cat, Repl)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUInputData, ALUOutputData
+from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp