- super().__init__(pspec)
- self.a = Signal(64, reset_less=True) # RA
- self.b = Signal(64, reset_less=True) # RB/immediate
- self.xer_so = Signal(reset_less=True) # XER bit 32: SO
- self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-
- def __iter__(self):
- yield from super().__iter__()
- yield self.a
- yield self.b
- yield self.xer_ca
- yield self.xer_so
-
- def eq(self, i):
- lst = super().eq(i)
- return lst + [self.a.eq(i.a), self.b.eq(i.b),
- self.xer_ca.eq(i.xer_ca),
- self.xer_so.eq(i.xer_so)]
-
-# TODO: ALUIntermediateData which does not have
-# cr0, ov, ov32 in it (because they are generated as outputs by
-# the final output stage, not by the intermediate stage)
-# https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
-
-class ALUOutputData(IntegerData):
- regspec = [('INT', 'o', '0:63'),
- ('CR', 'cr0', '0:3'),
- ('XER', 'xer_ca', '34,45'),
- ('XER', 'xer_ov', '33,44'),
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+ @property
+ def regspec(self):
+ return [('INT', 'o', self.intrange),
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
+ ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32