Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 4039096ab4d6c8b7b4d9f247b1011d5c64a47a3d..572ec9a6bcd18c22202f4a100531e6f843975889 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,33 +1,38 @@
-from nmigen import Signal, Const, Cat

 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.alu.alu_input_record import CompALUOpSubset

-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec

 
 
 
 

-class ALUInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'), # RA
-               ('INT', 'rb', '0:63'), # RB/immediate
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+class ALUInputData(FUBaseData):

     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 

+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32

 
 

-class ALUOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
-               ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
-               ('XER', 'xer_so', '32')]
+
+
+class ALUOutputData(FUBaseData):

     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 

+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
+               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
+               ('XER', 'xer_so', '32')]
+
+

 
 class ALUPipeSpec(CommonPipeSpec):
 
 class ALUPipeSpec(CommonPipeSpec):

-    regspec = (ALUInputData.regspec, ALUOutputData.regspec)

     opsubsetkls = CompALUOpSubset
     opsubsetkls = CompALUOpSubset

+    regspecklses = (ALUInputData, ALUOutputData)