- super().__init__(pspec)
- self.o = Data(64, name="stage_o")
- self.cr0 = Data(4, name="cr0")
- self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
- self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
- self.xer_so = Data(1, name="xer_so")
-
- def __iter__(self):
- yield from super().__iter__()
- yield self.o
- yield self.xer_ca
- yield self.cr0
- yield self.xer_ov
- yield self.xer_so
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+ @property
+ def regspec(self):
+ return [('INT', 'o', self.intrange),
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
+ ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
+ ('XER', 'xer_so', '32')]