rename regspecs to give a consistent naming scheme

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 7aa2fed2885ea32c154feec85979be72067d5281..b9423944877d54a8bb4113f4dce8a44dc5e6e9a1 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,71 +1,59 @@
-from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from nmigen import Signal, Const, Cat
 from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
 
 
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
-
-    def ports(self):
-        return self.ctx.ports()
-
-
 class ALUInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),
-               ('INT', 'b', '0:63'),
+    regspec = [('INT', 'ra', '0:63'),
+               ('INT', 'rb', '0:63'),
                ('XER', 'xer_so', '32'),
                ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.b = Signal(64, reset_less=True) # RB/immediate
+        self.ra = Signal(64, reset_less=True) # RA
+        self.rb = Signal(64, reset_less=True) # RB/immediate
         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+        # convenience
+        self.a, self.b = self.ra, self.rb
 
     def __iter__(self):
         yield from super().__iter__()
-        yield self.a
-        yield self.b
+        yield self.ra
+        yield self.rb
         yield self.xer_ca
         yield self.xer_so
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.a.eq(i.a), self.b.eq(i.b),
+        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
                       self.xer_ca.eq(i.xer_ca),
                       self.xer_so.eq(i.xer_so)]
 
 
 class ALUOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),
-               ('CR', 'cr0', '0:3'),
+               ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_ca', '34,45'),
                ('XER', 'xer_ov', '33,44'),
                ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.o = Signal(64, reset_less=True, name="stage_o")
-        self.cr0 = Data(4, name="cr0")
+        self.o = Data(64, name="stage_o")
+        self.cr_a = Data(4, name="cr_a")
         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
         self.xer_so = Data(1, name="xer_so")
+        # convenience
+        self.cr0 = self.cr_a
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
         yield self.xer_ca
-        yield self.cr0
+        yield self.cr_a
         yield self.xer_ov
         yield self.xer_so
 
@@ -73,20 +61,14 @@ class ALUOutputData(IntegerData):
         lst = super().eq(i)
         return lst + [self.o.eq(i.o),
                       self.xer_ca.eq(i.xer_ca),
-                      self.cr0.eq(i.cr0),
+                      self.cr_a.eq(i.cr_a),
                       self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
 
 
-class IntPipeSpec:
-    def __init__(self, id_wid=2, op_wid=1):
-        self.id_wid = id_wid
-        self.op_wid = op_wid
-        self.opkls = lambda _: CompALUOpSubset(name="op")
-        self.stage = None
-
-
-class ALUPipeSpec(IntPipeSpec):
+class ALUPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
-    def __init__(self, id_wid, op_wid):
-        super().__init__(id_wid, op_wid)
-        self.pipekls = SimpleHandshakeRedir
+    opsubsetkls = CompALUOpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO