-from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from nmigen import Signal, Const, Cat
from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
- def __init__(self, pspec):
- self.ctx = FPPipeContext(pspec)
- self.muxid = self.ctx.muxid
-
- def __iter__(self):
- yield from self.ctx
-
- def eq(self, i):
- return [self.ctx.eq(i.ctx)]
-
- def ports(self):
- return self.ctx.ports()
+from soc.decoder.power_decoder2 import Data
class ALUInputData(IntegerData):
+ regspec = [('INT', 'ra', '0:63'),
+ ('INT', 'rb', '0:63'),
+ ('XER', 'xer_so', '32'),
+ ('XER', 'xer_ca', '34,45')]
def __init__(self, pspec):
super().__init__(pspec)
- self.a = Signal(64, reset_less=True) # RA
- self.b = Signal(64, reset_less=True) # RB/immediate
- self.so = Signal(reset_less=True)
- self.carry_in = Signal(reset_less=True)
+ self.ra = Signal(64, reset_less=True) # RA
+ self.rb = Signal(64, reset_less=True) # RB/immediate
+ self.xer_so = Signal(reset_less=True) # XER bit 32: SO
+ self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+ # convenience
+ self.a, self.b = self.ra, self.rb
def __iter__(self):
yield from super().__iter__()
- yield self.a
- yield self.b
- yield self.carry_in
- yield self.so
+ yield self.ra
+ yield self.rb
+ yield self.xer_ca
+ yield self.xer_so
def eq(self, i):
lst = super().eq(i)
- return lst + [self.a.eq(i.a), self.b.eq(i.b),
- self.carry_in.eq(i.carry_in),
- self.so.eq(i.so)]
+ return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
+ self.xer_ca.eq(i.xer_ca),
+ self.xer_so.eq(i.xer_so)]
-# TODO: ALUIntermediateData which does not have
-# cr0, ov, ov32 in it (because they are generated as outputs by
-# the final output stage, not by the intermediate stage)
-# https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
class ALUOutputData(IntegerData):
+ regspec = [('INT', 'o', '0:63'),
+ ('CR', 'cr_a', '0:3'),
+ ('XER', 'xer_ca', '34,45'),
+ ('XER', 'xer_ov', '33,44'),
+ ('XER', 'xer_so', '32')]
def __init__(self, pspec):
super().__init__(pspec)
- self.o = Signal(64, reset_less=True, name="stage_o")
- self.carry_out = Signal(reset_less=True)
- self.carry_out32 = Signal(reset_less=True)
- self.cr0 = Signal(4, reset_less=True)
- self.ov = Signal(reset_less=True)
- self.ov32 = Signal(reset_less=True)
- self.so = Signal(reset_less=True)
+ self.o = Data(64, name="stage_o")
+ self.cr_a = Data(4, name="cr_a")
+ self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
+ self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
+ self.xer_so = Data(1, name="xer_so")
+ # convenience
+ self.cr0 = self.cr_a
def __iter__(self):
yield from super().__iter__()
yield self.o
- yield self.carry_out
- yield self.carry_out32
- yield self.cr0
- yield self.ov
- yield self.ov32
- yield self.so
+ yield self.xer_ca
+ yield self.cr_a
+ yield self.xer_ov
+ yield self.xer_so
def eq(self, i):
lst = super().eq(i)
return lst + [self.o.eq(i.o),
- self.carry_out.eq(i.carry_out),
- self.carry_out32.eq(i.carry_out32),
- self.cr0.eq(i.cr0), self.ov.eq(i.ov),
- self.ov32.eq(i.ov32), self.so.eq(i.so)]
-
-
-class IntPipeSpec:
- def __init__(self, id_wid=2, op_wid=1):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: CompALUOpSubset(name="op")
- self.stage = None
-
-
-class ALUPipeSpec(IntPipeSpec):
- def __init__(self, id_wid, op_wid):
- super().__init__(id_wid, op_wid)
- self.pipekls = SimpleHandshakeRedir
+ self.xer_ca.eq(i.xer_ca),
+ self.cr_a.eq(i.cr_a),
+ self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
+
+
+class ALUPipeSpec(CommonPipeSpec):
+ regspec = (ALUInputData.regspec, ALUOutputData.regspec)
+ opsubsetkls = CompALUOpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO
projects / soc.git / blobdiff