adjust syntax of SVP64 predicate test cas

[soc.git] / src / soc / fu / alu / test / svp64_cases.py

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 4ae5e8aeaae4c864e530f86ac742be3a1201dd47..3b42ef4ae24a5db43dad5baf9a20647270bfd5da 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -228,7 +228,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # expected results:
         # r5 = 0x0                   dest r3 is 0b10: skip
         # r6 = 0xffff_ffff_ffff_ff91 2nd bit of r3 is 1
-        isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'])
+        isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)