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mass-rename of modules to soc.fu.*
[soc.git]
/
src
/
soc
/
fu
/
branch
/
input_stage.py
diff --git
a/src/soc/fu/branch/input_stage.py
b/src/soc/fu/branch/input_stage.py
index e6ab48ea32dba22bf55831b33b42891118b524e1..e0f1b34bb549838be8d0ed25754b24a9b92eea9a 100644
(file)
--- a/
src/soc/fu/branch/input_stage.py
+++ b/
src/soc/fu/branch/input_stage.py
@@
-6,7
+6,7
@@
from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
unsigned)
from nmutil.pipemodbase import PipeModBase
from soc.decoder.power_enums import InternalOp
-from soc.alu.pipe_data import ALUInputData
+from soc.
fu.
alu.pipe_data import ALUInputData
from soc.decoder.power_enums import CryIn