from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
+from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.regfile.regfiles import FastRegs
+from soc.fu.test.common import TestCase, ALUHelpers
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
+from soc.regfile.util import fast_reg_to_spr # HACK!
-class TestCase:
- def __init__(self, program, regs, sprs, cr, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
- self.cr = cr
def get_rec_width(rec):
recwidth = 0
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to BranchFunctionUnit input regspec
+ """
+ res = {}
+
+ # CIA (PC)
+ res['cia'] = sim.pc.CIA.value
+
+ yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
+ yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2)
+
+ print ("get inputs", res)
+ return res
class BranchTestCase(FHDLTestCase):
+ test_data = []
def __init__(self, name):
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32,
- initial_sprs={}, initial_cr=0):
- tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
- self.test_name)
- test_data.append(tc)
+
+ def run_tst_program(self, prog, initial_regs=None,
+ initial_sprs=None, initial_cr=0):
+ tc = TestCase(prog, self.test_name,
+ initial_regs, initial_sprs, initial_cr)
+ self.test_data.append(tc)
def test_unconditional(self):
choices = ["b", "ba", "bl", "bla"]
initial_sprs=initial_sprs,
initial_cr=cr)
+ def test_bc_reg(self):
+ # XXX: bcctr and bcctrl time out (irony: they're counters)
+ choices = ["bclr", "bclrl", "bcctr", "bcctrl", "bctar", "bctarl"]
+ for insn in choices:
+ for i in range(20):
+ bh = random.randrange(0, 3)
+ bo = random.choice([4, 12])
+ bi = random.randrange(0, 31)
+ cr = random.randrange(0, (1<<32)-1)
+ ctr = random.randint(0, (1<<32)-1)
+ lr = random.randint(0, (1<<64)-1) & ~3
+ tar = random.randint(0, (1<<64)-1) & ~3
+ lst = [f"{insn} {bo}, {bi}, {bh}"]
+ initial_sprs={9: SelectableInt(ctr, 64),
+ 8: SelectableInt(lr, 64),
+ 815: SelectableInt(tar, 64)}
+ self.run_tst_program(Program(lst),
+ initial_sprs=initial_sprs,
+ initial_cr=cr)
+
def test_ilang(self):
pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+ simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr)
initial_cia = 0x2000
simulator.set_pc(initial_cia)
gen = program.generate_instructions()
# ask the decoder to decode this binary data (endian'd)
yield pdecode2.dec.bigendian.eq(0) # little / big?
yield instruction.eq(ins) # raw binary instr.
- yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
- yield branch.p.data_i.cr.eq(simulator.cr.get_range().value)
# note, here, the op will need further decoding in order
# to set the correct SPRs on SPR1/2/3. op_bc* require
- # spr2 to be set to CTR, op_bctar require spr1 to be
- # set to TAR, op_bclr* require spr1 to be set to LR.
+ # spr1 to be set to CTR, op_bctar require spr2 to be
+ # set to TAR, op_bclr* require spr2 to be set to LR.
# if op_sc*, op_rf* and op_hrfid are to be added here
# then additional op-decoding is required, accordingly
- yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value)
- print(f"cr0: {simulator.crl[0].get_range()}")
yield Settle()
+ yield from self.set_inputs(branch, pdecode2, simulator)
fn_unit = yield pdecode2.e.fn_unit
self.assertEqual(fn_unit, Function.BRANCH.value, code)
yield
self.assertEqual(branch_taken, sim_branch_taken, code)
if branch_taken:
branch_addr = yield branch.n.data_o.nia.data
+ print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}")
self.assertEqual(branch_addr, sim.pc.CIA.value, code)
+ # TODO: check write_fast1 as well (should contain CTR)
+
+ # TODO: this should be checking write_fast2
lk = yield dec2.e.lk
branch_lk = yield branch.n.data_o.lr.ok
self.assertEqual(lk, branch_lk, code)
branch_lr = yield branch.n.data_o.lr.data
self.assertEqual(sim.spr['LR'], branch_lr, code)
+ def set_inputs(self, branch, dec2, sim):
+ print(f"cr0: {sim.crl[0].get_range()}")
+
+ inp = yield from get_cu_inputs(dec2, sim)
+
+ yield from ALUHelpers.set_cia(branch, dec2, inp)
+ yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+ yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+ yield from ALUHelpers.set_cr_a(branch, dec2, inp)
+
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(BranchTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff