from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.isa.all import ISA
from soc.regfile.regfiles import FastRegs
+from soc.fu.test.common import TestCase, ALUHelpers
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
from soc.regfile.util import fast_reg_to_spr # HACK!
-class TestCase:
- def __init__(self, program, regs, sprs, cr, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
- self.cr = cr
def get_rec_width(rec):
recwidth = 0
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to BranchFunctionUnit input regspec
+ """
+ res = {}
+
+ # CIA (PC)
+ res['cia'] = sim.pc.CIA.value
+
+ yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
+ yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2)
+
+ print ("get inputs", res)
+ return res
class BranchTestCase(FHDLTestCase):
+ test_data = []
def __init__(self, name):
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32,
- initial_sprs={}, initial_cr=0):
- tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
- self.test_name)
- test_data.append(tc)
+
+ def run_tst_program(self, prog, initial_regs=None,
+ initial_sprs=None, initial_cr=0):
+ tc = TestCase(prog, self.test_name,
+ initial_regs, initial_sprs, initial_cr)
+ self.test_data.append(tc)
def test_unconditional(self):
choices = ["b", "ba", "bl", "bla"]
initial_sprs=initial_sprs,
initial_cr=cr)
-
-
def test_ilang(self):
pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+ simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr)
initial_cia = 0x2000
simulator.set_pc(initial_cia)
gen = program.generate_instructions()
# ask the decoder to decode this binary data (endian'd)
yield pdecode2.dec.bigendian.eq(0) # little / big?
yield instruction.eq(ins) # raw binary instr.
- yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
# note, here, the op will need further decoding in order
# to set the correct SPRs on SPR1/2/3. op_bc* require
# spr1 to be set to CTR, op_bctar require spr2 to be
branch_lr = yield branch.n.data_o.lr.data
self.assertEqual(sim.spr['LR'], branch_lr, code)
- def get_inputs(self, dec2, sim):
- """naming (res) must conform to BranchFunctionUnit input regspec
- """
- res = {}
-
- # CIA (PC)
- res['cia'] = sim.pc.CIA.value
-
- # CR A
- cr1_en = yield dec2.e.read_cr1.ok
- if cr1_en:
- cr1_sel = yield dec2.e.read_cr1.data
- res['cr_a'] = sim.crl[cr1_sel].get_range().value
-
- # Fast1
- spr_ok = yield dec2.e.read_fast1.ok
- spr_num = yield dec2.e.read_fast1.data
- # HACK
- spr_num = fast_reg_to_spr(spr_num)
- if spr_ok:
- res['spr1'] = sim.spr[spr_dict[spr_num].SPR].value
-
- # SPR2
- spr_ok = yield dec2.e.read_fast2.ok
- spr_num = yield dec2.e.read_fast2.data
- # HACK
- spr_num = fast_reg_to_spr(spr_num)
- if spr_ok:
- res['spr2'] = sim.spr[spr_dict[spr_num].SPR].value
-
- print ("get inputs", res)
- return res
-
def set_inputs(self, branch, dec2, sim):
- yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
print(f"cr0: {sim.crl[0].get_range()}")
- # TODO: this needs to now be read_fast1.data and read_fast2.data
- fast1_en = yield dec2.e.read_fast1.ok
- if fast1_en:
- fast1_sel = yield dec2.e.read_fast1.data
- spr1_sel = fast_reg_to_spr(fast1_sel)
- spr1_data = sim.spr[spr1_sel].value
- yield branch.p.data_i.spr1.eq(spr1_data)
-
- fast2_en = yield dec2.e.read_fast2.ok
- if fast2_en:
- fast2_sel = yield dec2.e.read_fast2.data
- spr2_sel = fast_reg_to_spr(fast2_sel)
- spr2_data = sim.spr[spr2_sel].value
- yield branch.p.data_i.spr2.eq(spr2_data)
-
+ inp = yield from get_cu_inputs(dec2, sim)
- cr_en = yield dec2.e.read_cr1.ok
- if cr_en:
- cr_sel = yield dec2.e.read_cr1.data
- cr = sim.crl[cr_sel].get_range().value
- yield branch.p.data_i.cr.eq(cr)
- full_cr = sim.cr.get_range().value
- print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+ yield from ALUHelpers.set_cia(branch, dec2, inp)
+ yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+ yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+ yield from ALUHelpers.set_cr_a(branch, dec2, inp)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(BranchTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff