whoops missed some cases in unit test changing ALUHelpers

[soc.git] / src / soc / fu / branch / test / test_pipe_caller.py

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 99913dcbc8ee82e2861c5288ca69c6ca6ca6519c..2c1e5b0d19019a0546f9988d77cfa8c1054b47b1 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.regfile.regfiles import FastRegs
 
-from soc.fu.test.common import TestCase
+from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
 import random
@@ -56,25 +56,9 @@ def get_cu_inputs(dec2, sim):
     # CIA (PC)
     res['cia'] = sim.pc.CIA.value
 
-    fast1_en = yield dec2.e.read_fast1.ok
-    if fast1_en:
-        fast1_sel = yield dec2.e.read_fast1.data
-        spr1_sel = fast_reg_to_spr(fast1_sel)
-        spr1_data = sim.spr[spr1_sel].value
-        res['spr1'] = spr1_data
-
-    fast2_en = yield dec2.e.read_fast2.ok
-    if fast2_en:
-        fast2_sel = yield dec2.e.read_fast2.data
-        spr2_sel = fast_reg_to_spr(fast2_sel)
-        spr2_data = sim.spr[spr2_sel].value
-        res['spr2'] = spr2_data
-
-    cr_en = yield dec2.e.read_cr1.ok
-    if cr_en:
-        cr_sel = yield dec2.e.read_cr1.data
-        cr = sim.crl[cr_sel].get_range().value
-        res['cr_a'] = cr
+    yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
+    yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
+    yield from ALUHelpers.get_sim_cr_a(res, sim, dec2)
 
     print ("get inputs", res)
     return res
@@ -181,7 +165,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                                test.mem, test.msr)
                 initial_cia = 0x2000
                 simulator.set_pc(initial_cia)
                 gen = program.generate_instructions()
@@ -247,14 +232,10 @@ class TestRunner(FHDLTestCase):
 
         inp = yield from get_cu_inputs(dec2, sim)
 
-        if 'cia' in inp:
-            yield branch.p.data_i.cia.eq(inp['cia'])
-        if 'spr1' in inp:
-            yield branch.p.data_i.spr1.eq(inp['spr1'])
-        if 'spr2' in inp:
-            yield branch.p.data_i.spr2.eq(inp['spr2'])
-        if 'cr_a' in inp:
-            yield branch.p.data_i.cr.eq(inp['cr_a'])
+        yield from ALUHelpers.set_cia(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+        yield from ALUHelpers.set_cr_a(branch, dec2, inp)
 
 
 if __name__ == "__main__":