big reorg on PowerDecoder2, actually Decode2Execute1Type

[soc.git] / src / soc / fu / branch / test / test_pipe_caller.py

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 2c1e5b0d19019a0546f9988d77cfa8c1054b47b1..f9582323faf3bc8658998f278632580e792123a3 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -191,7 +191,7 @@ class TestRunner(FHDLTestCase):
                     # then additional op-decoding is required, accordingly
                     yield Settle()
                     yield from self.set_inputs(branch, pdecode2, simulator)
-                    fn_unit = yield pdecode2.e.fn_unit
+                    fn_unit = yield pdecode2.e.do.fn_unit
                     self.assertEqual(fn_unit, Function.BRANCH.value, code)
                     yield
                     yield
@@ -220,7 +220,7 @@ class TestRunner(FHDLTestCase):
         # TODO: check write_fast1 as well (should contain CTR)
 
         # TODO: this should be checking write_fast2
-        lk = yield dec2.e.lk
+        lk = yield dec2.e.do.lk
         branch_lk = yield branch.n.data_o.lr.ok
         self.assertEqual(lk, branch_lk, code)
         if lk: