# generation for subtraction, should happen here
from nmigen import (Module, Signal)
from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import MicrOp
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import CryIn
class CommonInputStage(PipeModBase):
else:
comb += a.eq(self.i.a)
- comb += self.o.a.eq(a)
+ # SV zeroing on predicate source zeros the input
+ with m.If(~op.sv_pred_sz):
+ comb += self.o.a.eq(a)
##### operand B #####
else:
comb += b.eq(self.i.b)
- comb += self.o.b.eq(b)
+ # SV zeroing on predicate source zeros the input
+ with m.If(~op.sv_pred_sz):
+ comb += self.o.b.eq(b)
##### carry-in #####
##### sticky overflow and context (both pass-through) #####
if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
- with m.If(op.oe.oe_ok):
- comb += self.o.xer_so.eq(self.i.xer_so)
+ comb += self.o.xer_so.eq(self.i.xer_so)
comb += self.o.ctx.eq(self.i.ctx)
return m