Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index e36b14db340905cdf097cd084f1f3e9a0a6ca007..53e023ad6bb68d289bacccc9f5f627936961753e 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -3,8 +3,8 @@
 # generation for subtraction, should happen here
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import MicrOp
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import CryIn
 
 
 class CommonInputStage(PipeModBase):
@@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += a.eq(self.i.a)
 
-        comb += self.o.a.eq(a)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.a.eq(a)
 
         ##### operand B #####
 
@@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += b.eq(self.i.b)
 
-        comb += self.o.b.eq(b)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.b.eq(b)
 
         ##### carry-in #####