msr and pc moved to "state" in PowerDecode2

[soc.git] / src / soc / fu / compunits / test / test_compunit.py

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 393e445b591a7fa70a7cd847a63167119f4fbcf2..3af4bb501ea8dc31a585b28e4b7299b7b998cb96 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -209,8 +209,8 @@ class TestRunner(FHDLTestCase):
 
             # ask the decoder to decode this binary data (endian'd)
             yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
-            yield pdecode2.msr.eq(msr)  # set MSR "state"
-            yield pdecode2.cia.eq(pc)  # set PC "state"
+            yield pdecode2.state.msr.eq(msr)  # set MSR "state"
+            yield pdecode2.state.pc.eq(pc)  # set PC "state"
             yield instruction.eq(ins)          # raw binary instr.
             yield Settle()
             # debugging issue with branch