res[i] = inp[wrop]
return res
+def setup_test_memory(l0, sim):
+ mem = l0.mem.mem
+ print ("before, init mem", mem.depth, mem.width, mem)
+ for i in range(mem.depth):
+ data = sim.mem.ld(i*8, 8, False)
+ print ("init ", i, hex(data))
+ yield mem._array[i].eq(data)
+ yield Settle()
+ for k, v in sim.mem.mem.items():
+ print (" %6x %016x" % (k, v))
+ print ("before, nmigen mem dump")
+ for i in range(mem.depth):
+ actual_mem = yield mem._array[i]
+ print (" %6i %016x" % (i, actual_mem))
+
+
+def check_sim_memory(dut, l0, sim, code):
+ mem = l0.mem.mem
+ print ("sim mem dump")
+ for k, v in sim.mem.mem.items():
+ print (" %6x %016x" % (k, v))
+ print ("nmigen mem dump")
+ for i in range(mem.depth):
+ actual_mem = yield mem._array[i]
+ print (" %6i %016x" % (i, actual_mem))
+
+ for i in range(mem.depth):
+ expected_mem = sim.mem.ld(i*8, 8, False)
+ actual_mem = yield mem._array[i]
+ dut.assertEqual(expected_mem, actual_mem,
+ "%s %d %x %x" % (code, i,
+ expected_mem, actual_mem))
class TestRunner(FHDLTestCase):
def __init__(self, test_data, fukls, iodef, funit):
instruction = Signal(32)
pdecode = create_pdecode()
-
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+
+ # copy of the decoder for simulator
+ simdec = create_pdecode()
+ simdec2 = PowerDecode2(simdec)
+ m.submodules.simdec2 = simdec2 # pain in the neck
+
if self.funit == Function.LDST:
from soc.experiment.l0_cache import TstL0CacheBuffer
- m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64)
+ m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
+ addrwid=3)
pi = l0.l0.dports[0].pi
- m.submodules.cu = cu = self.fukls(pi, awid=4)
+ m.submodules.cu = cu = self.fukls(pi, awid=3)
m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
else:
program = test.program
self.subTest(test.name)
print ("test", test.name, test.mem)
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
+ gen = list(program.generate_instructions())
+ insncode = program.assembly.splitlines()
+ instructions = list(zip(gen, insncode))
+ sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
+ test.msr,
+ initial_insns=gen, respect_pc=False,
+ disassembly=insncode)
# initialise memory
if self.funit == Function.LDST:
- mem = l0.mem.mem
- for i in range(mem.depth//2):
- data = sim.mem.ld(i*16, 8)
- data1 = sim.mem.ld(i*16+8, 8)
- yield mem._array[i].eq(data | (data1<<32))
- print ("init mem", mem.depth, mem.width, mem)
+ yield from setup_test_memory(l0, sim)
index = sim.pc.CIA.value//4
while index < len(instructions):
ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
+ yield from sim.setup_one()
print(code)
# ask the decoder to decode this binary data (endian'd)
bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
# call simulated operation
- opname = code.split(' ')[0]
- yield from sim.call(opname)
+ yield from sim.execute_one()
index = sim.pc.CIA.value//4
yield Settle()
# sigh. hard-coded. test memory
if self.funit == Function.LDST:
- mem = l0.mem.mem
- print ("sim mem dump")
- for k, v in sim.mem.mem.items():
- print (" %6x %016x" % (k, v))
- print ("nmigen mem dump")
- for i in range(mem.depth//2):
- actual_mem = yield mem._array[i]
- print (" %6i %032x" % (i*2, actual_mem))
-
- for i in range(mem.depth//2):
- data = sim.mem.ld(i*16, 8)
- data1 = sim.mem.ld(i*16+8, 8)
- expected_mem = (data | (data1<<32))
- actual_mem = yield mem._array[i]
- self.assertEqual(expected_mem, actual_mem,
- "%s %d %x %x" % (code, i,
- expected_mem, actual_mem))
+ yield from check_sim_memory(self, l0, sim, code)
sim.add_sync_process(process)