-from nmigen import Module, Signal
+from nmigen import Module, Signal, ResetSignal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
+from soc.decoder.power_enums import Function
from soc.decoder.isa.all import ISA
-from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
from soc.experiment.compalu_multi import find_ok # hack
-import random
+
def set_cu_input(cu, idx, data):
rdop = cu.get_in_name(idx)
yield
yield cu.wr.go[idx].eq(0)
print ("result", repr(code), idx, wrop, wrok, hex(result))
+
return result
def get_cu_outputs(cu, code):
res = {}
+ wrmask = yield cu.wrmask
+ print ("get_cu_outputs", cu.n_dst, wrmask)
+ if not wrmask: # no point waiting (however really should doublecheck wr.rel)
+ return {}
+ # wait for at least one result
+ while True:
+ wr_rel_o = yield cu.wr.rel
+ if wr_rel_o:
+ break
+ yield
for i in range(cu.n_dst):
wr_rel_o = yield cu.wr.rel[i]
if wr_rel_o:
res[i] = inp[wrop]
return res
+def setup_test_memory(l0, sim):
+ mem = l0.mem.mem
+ print ("before, init mem", mem.depth, mem.width, mem)
+ for i in range(mem.depth):
+ data = sim.mem.ld(i*8, 8, False)
+ print ("init ", i, hex(data))
+ yield mem._array[i].eq(data)
+ yield Settle()
+ for k, v in sim.mem.mem.items():
+ print (" %6x %016x" % (k, v))
+ print ("before, nmigen mem dump")
+ for i in range(mem.depth):
+ actual_mem = yield mem._array[i]
+ print (" %6i %016x" % (i, actual_mem))
+
+
+def check_sim_memory(dut, l0, sim, code):
+ mem = l0.mem.mem
+ print ("sim mem dump")
+ for k, v in sim.mem.mem.items():
+ print (" %6x %016x" % (k, v))
+ print ("nmigen mem dump")
+ for i in range(mem.depth):
+ actual_mem = yield mem._array[i]
+ print (" %6i %016x" % (i, actual_mem))
+
+ for i in range(mem.depth):
+ expected_mem = sim.mem.ld(i*8, 8, False)
+ actual_mem = yield mem._array[i]
+ dut.assertEqual(expected_mem, actual_mem,
+ "%s %d %x %x" % (code, i,
+ expected_mem, actual_mem))
class TestRunner(FHDLTestCase):
def __init__(self, test_data, fukls, iodef, funit):
instruction = Signal(32)
pdecode = create_pdecode()
-
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- m.submodules.cu = cu = self.fukls()
+
+ # copy of the decoder for simulator
+ simdec = create_pdecode()
+ simdec2 = PowerDecode2(simdec)
+ m.submodules.simdec2 = simdec2 # pain in the neck
+
+ if self.funit == Function.LDST:
+ from soc.experiment.l0_cache import TstL0CacheBuffer
+ m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
+ addrwid=3)
+ pi = l0.l0.dports[0].pi
+ m.submodules.cu = cu = self.fukls(pi, awid=3)
+ m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
+ m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
+ else:
+ m.submodules.cu = cu = self.fukls()
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
print(test.name)
program = test.program
self.subTest(test.name)
- sim = ISA(pdecode2, test.regs, test.sprs, 0)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
+ print ("test", test.name, test.mem)
+ gen = list(program.generate_instructions())
+ insncode = program.assembly.splitlines()
+ instructions = list(zip(gen, insncode))
+ sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
+ test.msr,
+ initial_insns=gen, respect_pc=False,
+ disassembly=insncode)
+
+ # initialise memory
+ if self.funit == Function.LDST:
+ yield from setup_test_memory(l0, sim)
index = sim.pc.CIA.value//4
while index < len(instructions):
ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
+ yield from sim.setup_one()
print(code)
# ask the decoder to decode this binary data (endian'd)
"respec %s" % \
(bin(wr_rel_o), cu.rwid[1])
yield from set_cu_inputs(cu, inp)
- yield
rd_rel_o = yield cu.rd.rel
wr_rel_o = yield cu.wr.rel
wrmask = yield cu.wrmask
bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
# call simulated operation
- opname = code.split(' ')[0]
- yield from sim.call(opname)
+ yield from sim.execute_one()
index = sim.pc.CIA.value//4
yield Settle()
# get all outputs (one by one, just "because")
res = yield from get_cu_outputs(cu, code)
+ wrmask = yield cu.wrmask
+ rd_rel_o = yield cu.rd.rel
+ wr_rel_o = yield cu.wr.rel
+ print ("after got outputs, rd_rel, wr_rel, wrmask: ",
+ bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
+
+ # wait for busy to go low
+ while True:
+ busy_o = yield cu.busy_o
+ print ("busy", busy_o)
+ if not busy_o:
+ break
+ yield
yield from self.iodef.check_cu_outputs(res, pdecode2,
sim, code)
+ # sigh. hard-coded. test memory
+ if self.funit == Function.LDST:
+ yield from check_sim_memory(self, l0, sim, code)
+
+
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+
+ name = self.funit.name.lower()
+ with sim.write_vcd("%s_simulator.vcd" % name,
+ "%s_simulator.gtkw" % name,
traces=[]):
sim.run()
projects / soc.git / blobdiff