rename regspecs to give a consistent naming scheme

[soc.git] / src / soc / fu / compunits / test / test_cr_compunit.py

diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index b230be13d9ab6dd00358a4976536f6a28e83e498..5d502f9f93e4ad9d51e8c0591aebb0fd9233ea72 100644 (file)
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -41,25 +41,26 @@ class CRTestRunner(TestRunner):
                 cr3_sel = yield dec2.e.read_cr3.data
                 res['cr_c'] = sim.crl[cr3_sel].get_range().value
 
-        # RA
+        # RA/RC
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
-            res['a'] = sim.gpr(data1).value
+            res['ra'] = sim.gpr(data1).value
 
         # RB (or immediate)
         reg2_ok = yield dec2.e.read_reg2.ok
         if reg2_ok:
             data2 = yield dec2.e.read_reg2.data
-            res['b'] = sim.gpr(data2).value
+            res['rb'] = sim.gpr(data2).value
 
+        print ("get inputs", res)
         return res
 
     def check_cu_outputs(self, res, dec2, sim, code):
         """naming (res) must conform to CRFunctionUnit output regspec
         """
 
-        print ("check extra output", repr(code))
+        print ("check extra output", repr(code), res)
 
         # full CR
         whole_reg = yield dec2.e.write_cr_whole
@@ -67,13 +68,14 @@ class CRTestRunner(TestRunner):
         if whole_reg:
             full_cr = res['full_cr']
             expected_cr = sim.cr.get_range().value
+            print(f"expected cr {expected_cr:x}, actual: {full_cr:x}")
             self.assertEqual(expected_cr, full_cr, code)
 
         # part-CR
         if cr_en:
             cr_sel = yield dec2.e.write_cr.data
             expected_cr = sim.crl[cr_sel].get_range().value
-            real_cr = res['cr']
+            real_cr = res['cr_a']
             self.assertEqual(expected_cr, real_cr, code)
 
         # RT