noticed the regular pattern in all pipe_data.py (regspecs).

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 24402270c9ed0472d4a38689a3a1c6d6a807851d..00f24dbdf51c299ce806c807ce434521750fe6ee 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -15,61 +15,22 @@ class CRInputData(IntegerData):
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range

-               ('CR', 'cr_c', '0:3')]     # 4 bit range
+               ('CR', 'cr_c', '0:3')]     # 4 bit: for CR_OP partial update

     def __init__(self, pspec):
     def __init__(self, pspec):

-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB
-        self.full_cr = Signal(32, reset_less=True) # full CR in
-        self.cr_a = Signal(4, reset_less=True)
-        self.cr_b = Signal(4, reset_less=True)
-        self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
+        super().__init__(pspec, False)

         # convenience
         self.a, self.b = self.ra, self.rb
 
         # convenience
         self.a, self.b = self.ra, self.rb
 

-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.full_cr
-        yield self.cr_a
-        yield self.cr_b
-        yield self.cr_c
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_a.eq(i.cr_a),
-                      self.cr_b.eq(i.cr_b),
-                      self.cr_c.eq(i.cr_c)]
-                      

 
 class CROutputData(IntegerData):
 
 class CROutputData(IntegerData):

-    regspec = [('INT', 'o', '0:63'),      # 64 bit range
+    regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range

                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3')]     # 4 bit range
     def __init__(self, pspec):
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3')]     # 4 bit range
     def __init__(self, pspec):

-        super().__init__(pspec)
-        self.o = Data(64, name="o") # RA
-        self.full_cr = Data(32, name="full_cr")
-        self.cr_a = Data(4, name="cr_a")
+        super().__init__(pspec, True)

         # convenience
         self.cr = self.cr_a
 
         # convenience
         self.cr = self.cr_a
 

-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.full_cr
-        yield self.cr_a
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_a.eq(i.cr_a)]
-

 
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
 
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)