rename regspecs to give a consistent naming scheme

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index b16e56881bcc501982cb53faac459ab5e5cdefa5..a7291c6c3d4e1d6cec184193fff7bf6f86b7be4d 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -10,25 +10,27 @@ from soc.decoder.power_decoder2 import Data
 
 
 class CRInputData(IntegerData):
 
 
 class CRInputData(IntegerData):

-    regspec = [('INT', 'a', '0:63'),      # 64 bit range
-               ('INT', 'b', '0:63'),      # 6B bit range
+    regspec = [('INT', 'ra', '0:63'),      # 64 bit range
+               ('INT', 'rb', '0:63'),      # 64 bit range

                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
                ('CR', 'cr_c', '0:3')]     # 4 bit range
     def __init__(self, pspec):
         super().__init__(pspec)
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
                ('CR', 'cr_c', '0:3')]     # 4 bit range
     def __init__(self, pspec):
         super().__init__(pspec)

-        self.a = Signal(64, reset_less=True) # RA
-        self.b = Signal(64, reset_less=True) # RB
+        self.ra = Signal(64, reset_less=True) # RA
+        self.rb = Signal(64, reset_less=True) # RB

         self.full_cr = Signal(32, reset_less=True) # full CR in
         self.cr_a = Signal(4, reset_less=True)
         self.cr_b = Signal(4, reset_less=True)
         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
         self.full_cr = Signal(32, reset_less=True) # full CR in
         self.cr_a = Signal(4, reset_less=True)
         self.cr_b = Signal(4, reset_less=True)
         self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update

+        # convenience
+        self.a, self.b = self.ra, self.rb

 
     def __iter__(self):
         yield from super().__iter__()
 
     def __iter__(self):
         yield from super().__iter__()

-        yield self.a
-        yield self.b
+        yield self.ra
+        yield self.rb

         yield self.full_cr
         yield self.cr_a
         yield self.cr_b
         yield self.full_cr
         yield self.cr_a
         yield self.cr_b


@@ -36,8 +38,8 @@ class CRInputData(IntegerData):
 
     def eq(self, i):
         lst = super().eq(i)
 
     def eq(self, i):
         lst = super().eq(i)

-        return lst + [self.a.eq(i.a),
-                      self.b.eq(i.b),
+        return lst + [self.ra.eq(i.ra),
+                      self.rb.eq(i.rb),

                       self.full_cr.eq(i.full_cr),
                       self.cr_a.eq(i.cr_a),
                       self.cr_b.eq(i.cr_b),
                       self.full_cr.eq(i.full_cr),
                       self.cr_a.eq(i.cr_a),
                       self.cr_b.eq(i.cr_b),


@@ -47,24 +49,26 @@ class CRInputData(IntegerData):
 class CROutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),      # 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
 class CROutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),      # 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range

-               ('CR', 'cr', '0:3')]     # 4 bit range
+               ('CR', 'cr_a', '0:3')]     # 4 bit range

     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Data(64, name="o") # RA
         self.full_cr = Data(32, name="full_cr")
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Data(64, name="o") # RA
         self.full_cr = Data(32, name="full_cr")

-        self.cr = Data(4, name="cr")
+        self.cr_a = Data(4, name="cr_a")
+        # convenience
+        self.cr = self.cr_a

 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
         yield self.full_cr
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
         yield self.full_cr

-        yield self.cr
+        yield self.cr_a

 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.o.eq(i.o),
                       self.full_cr.eq(i.full_cr),
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.o.eq(i.o),
                       self.full_cr.eq(i.full_cr),

-                      self.cr.eq(i.cr)]
+                      self.cr_a.eq(i.cr_a)]

 
 
 class CRPipeSpec(CommonPipeSpec):
 
 
 class CRPipeSpec(CommonPipeSpec):