okaaay add a "rdflags" function which obtains the yes/no flags for each register...

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index c22a3b1ecd19172eb2a898b1df2dbb29e6f1fcee..b16e56881bcc501982cb53faac459ab5e5cdefa5 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -2,7 +2,7 @@
 Links:
 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 """
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from soc.fu.cr.cr_input_record import CompCROpSubset
@@ -70,3 +70,11 @@ class CROutputData(IntegerData):
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
     opsubsetkls = CompCROpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA/RC
+        reg2_ok = e.read_reg2.ok # RB
+        full_reg = e.read_cr_whole # full CR
+        cr1_en = e.read_cr1.ok # CR A
+        cr2_en = e.read_cr2.ok # CR B
+        cr3_en = e.read_cr3.ok # CR C
+        return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)