rename IntegerData to FUBaseData

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 06c7bfb7e8d209b4ed5570e35f71778b9c859901..edcad2e9aa6a1c84c53b0e73f5925eea7e981c30 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -2,11 +2,11 @@
 Links:
 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 """
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 from soc.fu.cr.cr_input_record import CompCROpSubset
 
 
-class CRInputData(IntegerData):
+class CRInputData(FUBaseData):
     regspec = [('INT', 'ra', '0:63'),      # 64 bit range
                ('INT', 'rb', '0:63'),      # 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
@@ -19,7 +19,7 @@ class CRInputData(IntegerData):
         self.a, self.b = self.ra, self.rb
 
 
-class CROutputData(IntegerData):
+class CROutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3')]     # 4 bit range