use copy of FHDLTestCase

[soc.git] / src / soc / fu / div / formal / proof_main_stage.py

diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py
index 456ff815348a80f243bcdeddf1d51d1fc78a5092..f3baa1b67257fe34b770822581829d87cda6a4bb 100644 (file)
--- a/src/soc/fu/div/formal/proof_main_stage.py
+++ b/src/soc/fu/div/formal/proof_main_stage.py
@@ -9,7 +9,7 @@ Links:
 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed)
 from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import rtlil