replace data_o with o_data and data_i with i_data as well

[soc.git] / src / soc / fu / div / test / helper.py

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index 15f9d8269d5c0d3a3feadcfbcb47e817664fdad7..98d2b9ed640b301129f02e61b0bfe85cb09003bb 100644 (file)
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -41,7 +41,7 @@ def get_cu_inputs(dec2, sim):
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
+    # and place it into i_data.b
 
     inp = yield from get_cu_inputs(dec2, sim)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
@@ -166,7 +166,7 @@ class DivTestHelper(unittest.TestCase):
         pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
         m.submodules.alu = alu = DivBasePipe(pspec)
 
-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -232,8 +232,8 @@ class DivTestHelper(unittest.TestCase):
         print("oe, oe_ok", oe, oe_ok)
         if not oe or not oe_ok:
             # if OE not enabled, XER SO and OV must not be activated
-            so_ok = yield alu.n.data_o.xer_so.ok
-            ov_ok = yield alu.n.data_o.xer_ov.ok
+            so_ok = yield alu.n.o_data.xer_so.ok
+            ov_ok = yield alu.n.o_data.xer_ov.ok
             print("so, ov", so_ok, ov_ok)
             self.assertEqual(ov_ok, False, code)
             self.assertEqual(so_ok, False, code)