use copy of FHDLTestCase

[soc.git] / src / soc / fu / logical / formal / proof_bpermd.py

diff --git a/src/soc/fu/logical/formal/proof_bpermd.py b/src/soc/fu/logical/formal/proof_bpermd.py
index e987f88b7955636287ab4e9984cfddc7c8d94f7d..02f6544276d5616bd9f561ad15d3237159e96569 100644 (file)
--- a/src/soc/fu/logical/formal/proof_bpermd.py
+++ b/src/soc/fu/logical/formal/proof_bpermd.py
@@ -4,7 +4,7 @@
 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed)
 from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from soc.fu.logical.bpermd import Bpermd