use copy of FHDLTestCase

[soc.git] / src / soc / fu / logical / formal / proof_input_stage.py

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index c80b6fb390df307b5cd39427fad4de42be49aa87..16f3df0432413d6eb963db6d945c88eb537368d2 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from soc.fu.alu.input_stage import ALUInputStage