use copy of FHDLTestCase

[soc.git] / src / soc / fu / logical / formal / proof_main_stage.py

diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py
index 6cb31ead0a045a8f059a712fb969e72dcee5503d..de1c788d4fbf482a15b72ce86053ca56ee8b828b 100644 (file)
--- a/src/soc/fu/logical/formal/proof_main_stage.py
+++ b/src/soc/fu/logical/formal/proof_main_stage.py
@@ -9,7 +9,7 @@ Links:
 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed)
 from nmigen.asserts import Assert, AnyConst, Assume, Cover
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import rtlil