replace data_o with o_data and data_i with i_data as well

[soc.git] / src / soc / fu / logical / test / test_pipe_caller.py

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index ca14b271d6958534961e9814a86b27df7a7e7b50..293682e3a12da7d36e865b41e0ebbd87b082a382 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -39,7 +39,7 @@ def get_cu_inputs(dec2, sim):
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
+    # and place it into i_data.b
 
     inp = yield from get_cu_inputs(dec2, sim)
     print ("set alu inputs", inp)
@@ -119,7 +119,7 @@ class TestRunner(FHDLTestCase):
         pspec = LogicalPipeSpec(id_wid=2)
         m.submodules.alu = alu = LogicalBasePipe(pspec)
 
-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)