convert to individual PipeSpecs for each pipeline

[soc.git] / src / soc / fu / logical / test / test_pipe_caller.py

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 4a2c09f094a4dd6f49ff613837755c9a0799a262..c14f6a08402f6a89b4aac83ce3f3763ba697c1b5 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -13,8 +13,7 @@ from soc.decoder.isa.all import ISA
 
 
 from soc.fu.logical.pipeline import LogicalBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.pipe_data import LogicalPipeSpec
 import random
 
 
@@ -181,9 +180,9 @@ class LogicalTestCase(FHDLTestCase):
             self.run_tst_program(Program(lst), initial_regs)
 
     def test_ilang(self):
-        rec = CompALUOpSubset()
+        rec = LogicalPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = LogicalBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
@@ -204,9 +203,9 @@ class TestRunner(FHDLTestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        rec = CompALUOpSubset()
+        rec = LogicalPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         m.submodules.alu = alu = LogicalBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)