priv_mode/virt_mode are set in the request, which is passed through

[soc.git] / src / soc / fu / mmu / fsm.py

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index f09fd987e311f80f72db005ddec4be26c7c437d9..373f2cc8a18169e2e94bc29955ca5ad865fbbbd9 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -108,8 +108,10 @@ class FSMMMUStage(ControlBase):
         comb += spr.eq(decode_spr_num(x_fields.SPR))
 
         # based on MSR bits, set priv and virt mode.  TODO: 32-bit mode
-        comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
-        comb += d_in.virt_mode.eq(msr_i[MSR.DR])
+        # XXX WARK-WARK, this should be done in loadstore.py
+        # (through the PortInterface)
+        #comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
+        #comb += d_in.virt_mode.eq(msr_i[MSR.DR])
         #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
 
         # ok so we have to "pulse" the MMU (or dcache) rather than