Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / mmu / fsm.py

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index c1d4d74f9113f19b02ecf4d43395a9f738d36087..24be3f5402710bed1fb3a016e672ef12cc13671b 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -225,6 +225,7 @@ class FSMMMUStage(ControlBase):
                     # from accepting any other LD/ST requests.
                     comb += valid.eq(1)   # start "pulse"
                     comb += ldst.instr_fault.eq(blip)
+                    comb += ldst.priv_mode.eq(~msr_i[MSR.PR])
                     comb += ldst.maddr.eq(cia_i)
                     # XXX should not access this!
                     comb += done.eq(ldst.done)