replace data_o with o_data and data_i with i_data as well

[soc.git] / src / soc / fu / mul / test / helper.py

diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py
index 06f1a56fa64ff0ad54e7242284b4c92a48a1e1cb..7266223a481493db884740bf62aa0c048c670dd8 100644 (file)
--- a/src/soc/fu/mul/test/helper.py
+++ b/src/soc/fu/mul/test/helper.py
@@ -42,7 +42,7 @@ def get_cu_inputs(dec2, sim):
 def set_alu_inputs(alu, dec2, sim, has_third_input):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
+    # and place it into i_data.b
 
     inp = yield from get_cu_inputs(dec2, sim)
     print("set alu inputs", inp)
@@ -151,7 +151,7 @@ class MulTestHelper(unittest.TestCase):
         pspec = MulPipeSpec(id_wid=2)
         m.submodules.alu = alu = MulBasePipe(pspec)
 
-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -183,8 +183,8 @@ class MulTestHelper(unittest.TestCase):
         oe_ok = yield dec2.e.do.oe.ok
         if not oe or not oe_ok:
             # if OE not enabled, XER SO and OV must correspondingly be false
-            so_ok = yield alu.n.data_o.xer_so.ok
-            ov_ok = yield alu.n.data_o.xer_ov.ok
+            so_ok = yield alu.n.o_data.xer_so.ok
+            ov_ok = yield alu.n.o_data.xer_ov.ok
             self.assertEqual(so_ok, False, code)
             self.assertEqual(ov_ok, False, code)