from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
+from nmigen.sim.pysim import Simulator, Delay, Settle
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
-
-from soc.fu.test.common import (TestCase, ALUHelpers)
+from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
from soc.fu.mul.pipeline import MulBasePipe
from soc.fu.mul.pipe_data import MulPipeSpec
import random
"""
res = {}
- yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
- yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
- yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
- yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+ yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
- print ("alu get_cu_inputs", res)
+ print("alu get_cu_inputs", res)
return res
-
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
# and place it into data_i.b
inp = yield from get_cu_inputs(dec2, sim)
- print ("set alu inputs", inp)
+ print("set alu inputs", inp)
yield from ALUHelpers.set_int_ra(alu, dec2, inp)
yield from ALUHelpers.set_int_rb(alu, dec2, inp)
- yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
yield from ALUHelpers.set_xer_so(alu, dec2, inp)
# takes around 3 seconds
-class MulTestCase(FHDLTestCase):
- test_data = []
-
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
-
- def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
- tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
- self.test_data.append(tc)
+class MulTestCase(TestAccumulatorBase):
- def tst_0_mullw(self):
+ def case_0_mullw(self):
lst = [f"mullw 3, 1, 2"]
initial_regs = [0] * 32
#initial_regs[1] = 0xffffffffffffffff
#initial_regs[2] = 0xffffffffffffffff
initial_regs[1] = 0x2ffffffff
initial_regs[2] = 0x2
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def tst_1_mullwo_(self):
+ def case_1_mullwo_(self):
lst = [f"mullwo. 3, 1, 2"]
initial_regs = [0] * 32
initial_regs[1] = 0x3b34b06f
initial_regs[2] = 0xfdeba998
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def tst_2_mullwo(self):
+ def case_2_mullwo(self):
lst = [f"mullwo 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = 0xffffffffffffa988 # -5678
- initial_regs[2] = 0xffffffffffffedcc # -1234
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = 0xffffffffffffa988 # -5678
+ initial_regs[2] = 0xffffffffffffedcc # -1234
+ self.add_case(Program(lst, bigendian), initial_regs)
- def tst_3_mullw(self):
+ def case_3_mullw(self):
lst = ["mullw 3, 1, 2",
"mullw 3, 1, 2"]
initial_regs = [0] * 32
initial_regs[1] = 0x6
initial_regs[2] = 0xe
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_4_mullw_rand(self):
+ def case_4_mullw_rand(self):
for i in range(40):
lst = ["mullw 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
- initial_regs[2] = random.randint(0, (1<<64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_4_mullw_nonrand(self):
+ def case_4_mullw_nonrand(self):
for i in range(40):
lst = ["mullw 3, 1, 2"]
initial_regs = [0] * 32
initial_regs[1] = i+1
initial_regs[2] = i+20
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def tst_rand_mullw(self):
+ def case_mulhw__regression_1(self):
+ lst = ["mulhw. 3, 1, 2"
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x7745b36eca6646fa
+ initial_regs[2] = 0x47dfba3a63834ba2
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_rand_mul_lh(self):
+ insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_rand_mullw(self):
insns = ["mullw", "mullw.", "mullwo", "mullwo."]
for i in range(40):
choice = random.choice(insns)
lst = [f"{choice} 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
- initial_regs[2] = random.randint(0, (1<<64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_ilang(self):
+ def case_rand_mulld(self):
+ insns = ["mulld", "mulld.", "mulldo", "mulldo."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_rand_mulhd(self):
+ insns = ["mulhd", "mulhd."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_0_mullhw_regression(self):
+ lst = [f"mulhwu 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x4000000000000000
+ initial_regs[2] = 0x0000000000000002
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+# TODO add test case for these 3 operand cases (madd
+# needs to be implemented)
+# "maddhd","maddhdu","maddld"
+
+ def case_ilang(self):
pspec = MulPipeSpec(id_wid=2)
alu = MulBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
f.write(vl)
-class TestRunner(FHDLTestCase):
+class TestRunner(unittest.TestCase):
def __init__(self, test_data):
super().__init__("run_all")
self.test_data = test_data
comb = m.d.comb
instruction = Signal(32)
- pdecode = create_pdecode()
+ fn_name = "MUL"
+ opkls = MulPipeSpec.opsubsetkls
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+ pdecode = pdecode2.dec
pspec = MulPipeSpec(id_wid=2)
m.submodules.alu = alu = MulBasePipe(pspec)
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print(test.name)
program = test.program
self.subTest(test.name)
sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
- test.mem, test.msr)
+ test.mem, test.msr,
+ bigendian=bigendian)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
yield Settle()
so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
- print ("before: so/ov/32", so, ov, ov32)
+ print("before: so/ov/32", so, ov, ov32)
# ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
fn_unit = yield pdecode2.e.do.fn_unit
yield Settle()
sim.add_sync_process(process)
- with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
+ traces=[]):
sim.run()
def check_alu_outputs(self, alu, dec2, sim, code):
- rc = yield dec2.e.do.rc.data
+ rc = yield dec2.e.do.rc.rc
cridx_ok = yield dec2.e.write_cr.ok
cridx = yield dec2.e.write_cr.data
- print ("check extra output", repr(code), cridx_ok, cridx)
+ print("check extra output", repr(code), cridx_ok, cridx)
if rc:
self.assertEqual(cridx, 0, code)
yield from ALUHelpers.get_cr_a(res, alu, dec2)
yield from ALUHelpers.get_xer_ov(res, alu, dec2)
- yield from ALUHelpers.get_xer_ca(res, alu, dec2)
yield from ALUHelpers.get_int_o(res, alu, dec2)
yield from ALUHelpers.get_xer_so(res, alu, dec2)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
- yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
ALUHelpers.check_int_o(self, res, sim_o, code)
ALUHelpers.check_xer_ov(self, res, sim_o, code)
- ALUHelpers.check_xer_ca(self, res, sim_o, code)
ALUHelpers.check_xer_so(self, res, sim_o, code)
ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(MulTestCase.test_data))
+ suite.addTest(TestRunner(MulTestCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff