from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim.pysim import Simulator, Delay, Settle
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
initial_regs[2] = 0x47dfba3a63834ba2
self.add_case(Program(lst, bigendian), initial_regs)
- def case_4_mullw_rand(self):
- for i in range(40):
- lst = ["mullw 3, 1, 2"]
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- initial_regs[2] = random.randint(0, (1 << 64)-1)
- self.add_case(Program(lst, bigendian), initial_regs)
-
def case_rand_mul_lh(self):
insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
for i in range(40):
initial_regs[2] = random.randint(0, (1 << 64)-1)
self.add_case(Program(lst, bigendian), initial_regs)
+ def case_0_mullhw_regression(self):
+ lst = [f"mulhwu 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x4000000000000000
+ initial_regs[2] = 0x0000000000000002
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+# TODO add test case for these 3 operand cases (madd
+# needs to be implemented)
+# "maddhd","maddhdu","maddld"
+
def case_ilang(self):
pspec = MulPipeSpec(id_wid=2)
alu = MulBasePipe(pspec)
comb = m.d.comb
instruction = Signal(32)
- pdecode = create_pdecode()
+ fn_name = "MUL"
+ opkls = MulPipeSpec.opsubsetkls
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+ pdecode = pdecode2.dec
pspec = MulPipeSpec(id_wid=2)
m.submodules.alu = alu = MulBasePipe(pspec)
def check_alu_outputs(self, alu, dec2, sim, code):
- rc = yield dec2.e.do.rc.data
+ rc = yield dec2.e.do.rc.rc
cridx_ok = yield dec2.e.write_cr.ok
cridx = yield dec2.e.write_cr.data