+ self.data = []
+ self.is_output = output
+ for i, (regfile, regname, widspec) in enumerate(self.regspec):
+ wid = get_regspec_bitwidth([self.regspec], 0, i)
+ if output:
+ sig = Data(wid, name=regname)
+ else:
+ sig = Signal(wid, name=regname, reset_less=True)
+ setattr(self, regname, sig)
+ self.data.append(sig)