Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 2be88375774ab054d77967c7586689d3c9e167eb..f5971aadff87b2cad67b9d6610ee929f2081f11f 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -17,16 +17,18 @@ which MultiCompUnit port, how wide the connection is, and so on.
 
 """
 from nmigen import Const
+from soc.regfile.regfiles import XERRegs, FastRegs
+
 
 def get_regspec_bitwidth(regspec, srcdest, idx):
-    print ("get_regspec_bitwidth", regspec, srcdest, idx)
+    print("get_regspec_bitwidth", regspec, srcdest, idx)
     bitspec = regspec[srcdest][idx]
     wid = 0
-    print (bitspec)
+    print(bitspec)
     for ranges in bitspec[2].split(","):
         ranges = ranges.split(":")
-        print (ranges)
-        if len(ranges) == 1: # only one bit
+        print(ranges)
+        if len(ranges) == 1:  # only one bit
             wid += 1
         else:
             start, end = map(int, ranges)
@@ -37,6 +39,7 @@ def get_regspec_bitwidth(regspec, srcdest, idx):
 class RegSpec:
     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
         self._rwid = rwid
+        print ("RegSpec", rwid)
         if isinstance(rwid, int):
             # rwid: integer (covers all registers)
             self._n_src, self._n_dst = n_src, n_dst
@@ -55,63 +58,55 @@ class RegSpec:
         return get_regspec_bitwidth(self._rwid, 0, i)
 
 
-class RegSpecALUAPI:
-    def __init__(self, rwid, alu):
+class RegSpecAPI:
+    def __init__(self, rwid):
         """RegSpecAPI
 
         * :rwid:       regspec
-        * :alu:        ALU covered by this regspec
         """
         self.rwid = rwid
-        self.alu = alu # actual ALU - set as a "submodule" of the CU
+
+    def get_io_spec(self, direction, i):
+        if direction: # input (read specs)
+            return self.get_in_spec(i)
+        return self.get_out_spec(i)
+
+    def get_in_spec(self, i):
+        return self.rwid[0][i]
+
+    def get_out_spec(self, i):
+        return self.rwid[1][i]
 
     def get_in_name(self, i):
-        return self.rwid[0][i][1]
+        return self.get_in_spec(i)[1]
 
     def get_out_name(self, i):
-        return self.rwid[1][i][1]
+        return self.get_out_spec(i)[1]
+
+
+class RegSpecALUAPI(RegSpecAPI):
+    def __init__(self, rwid, alu):
+        """RegSpecAPI
+
+        * :rwid:       regspec
+        * :alu:        ALU covered by this regspec
+        """
+        super().__init__(rwid)
+        self.alu = alu
 
     def get_out(self, i):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+        if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.out[i]
         # regspec-based API: look up variable through regspec thru row number
-        return getattr(self.alu.n.data_o, self.get_out_name(i))
+        return getattr(self.alu.n.o_data, self.get_out_name(i))
 
     def get_in(self, i):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+        if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.i[i]
         # regspec-based API: look up variable through regspec thru row number
-        return getattr(self.alu.p.data_i, self.get_in_name(i))
+        return getattr(self.alu.p.i_data, self.get_in_name(i))
 
     def get_op(self):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+        if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.op
-        return self.alu.p.data_i.ctx.op
-
-
-# function for the relationship between regspecs and Decode2Execute1Type
-def regspec_rdmask(e, regspec, idx):
-    (regfile, name, _) = regspec[idx]
-    if regfile == 'INT':
-        if name == 'ra': # RA
-            return e.read_reg1.ok
-        if name == 'rb': # RB
-            return e.read_reg2.ok
-        if name == 'rc': # RS
-            return e.read_reg3.ok
-    if regfile == 'CR':
-        if name == 'full_cr': # full CR
-            return e.read_cr_whole
-        if name == 'cr_a': # CR A
-            return e.read_cr1.ok
-        if name == 'cr_b': # CR B
-            return e.read_cr2.ok
-        if name == 'cr_c': # CR C
-            return e.read_cr3.ok
-    if regfile == 'XER':
-        if name in ['xer_so', 'xer_ov']:
-            return e.oe.oe & e.oe.oe_ok
-        if name == 'xer_ca':
-            return e.input_carry
-
-    assert False, "regspec rdmask not found", regspec, idx
+        return self.alu.p.i_data.ctx.op