Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index f6d90d9e35e1b7cced05fc36d073a8791241dab0..f5971aadff87b2cad67b9d6610ee929f2081f11f 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -39,6 +39,7 @@ def get_regspec_bitwidth(regspec, srcdest, idx):
 class RegSpec:
     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
         self._rwid = rwid
+        print ("RegSpec", rwid)
         if isinstance(rwid, int):
             # rwid: integer (covers all registers)
             self._n_src, self._n_dst = n_src, n_dst
@@ -65,6 +66,11 @@ class RegSpecAPI:
         """
         self.rwid = rwid
 
+    def get_io_spec(self, direction, i):
+        if direction: # input (read specs)
+            return self.get_in_spec(i)
+        return self.get_out_spec(i)
+
     def get_in_spec(self, i):
         return self.rwid[0][i]